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lowRISC

Open to the core - collaborative engineering for open source silicon and tools

c++chiselfpgahardwarelinuxverilogrisc-vpythonsystemverilog

Participation history

3 GSoC years

2020

2 projects

Official year page

Simulated memory controller

Project goal The goal of this project is to devise and implement a simulation-ready memory controller dedicated to benchmarking processor cores...

Proof-of-concept integration of pointer authentication support in Ibex

Pointer Authentication is a software security primitive that makes it much harder for an attacker to aggravate attacks targeting arbitrary code...

2017

4 projects

Official year page

CMSIS-DSP on PULPino

I will implement ARM CMSIS library on PULPino using proposed priority, then i will port the implementation to its DSP core and compare results.

Implementation of core lock step in the lowRISC SoC for use in cubesats.

The upgraded role of cubesats, fueled by technological advances in the aerospace industry, that lower launch costs, has opened access to space for a...

ORAM interface for RISC-V systems

Memory access is one of the most important operation done in modern processors thus it plays an important role in implementation of trusted execution...

RISC-V Simulator for education

This project aims to support the use of RISC-V in education by providing a simulator to step through assembly programs. This is a similar concept to...

2016

4 projects

Official year page

Integrate more open-source IP for lowRISC on FPGAs

To introduce open-source IP for components such as an NASTI slave memory mapped DDRx controller.

Arduino to PULPino library porting

PULPino is an open-source microcontroller system, based on a small 32-bit RISC-V core. Importing Arduino Libraries to PULPino architecture should...

Porting xv6 to the lowRISC platform

Xv6 is a “simple Unix-like teaching operating system”. It is based on Sixth Edition Unix and written in ANSI C for x86. Its simplicity coupled with...

Porting OPTEE to lowRISC

This project aims to port OPTEE for a RISC-V based machine by implementing trust-zone mechanisms using minion cores and tagged memory. Also OPTEE...