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Free and Open Source Silicon Foundation

Working together for Free and Open Source Silicon

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Participation history

11 GSoC years

20262025202420232022202120202019201820172016

2026

5 projects

Official year page

Surfer Memory and Wide Array Support

This proposal focuses on enhancing the Surfer waveform viewer by adding support for memory and wide array visualization. Current waveform views are...

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Using AI to Improve Open-Source IP

Millions of lines of open-source Verilog exist but remain verbose and hard to maintain. TL-Verilog offers a cleaner abstraction, but almost none of...

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Robust Implementation and Verification of the RISC-V Svadu Extension for Ariane+OpenPiton

This project aims to bring Ariane+OpenPiton closer to RISC-V RVA23 compliance by adding support for the Svadu extension. By enabling hardware-managed...

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Generate Counter Examples for Bounded Model Checks in CIRCT

circt-bmc can already prove when an assertion is falsifiable, but it does not yet produce the counterexample trace format hardware developers rely on...

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Generic MinimumLinuxBoot for RTL Simulations

Booting Linux in OpenPiton's Verilator RTL simulation takes days. This project builds a checkpoint/restore pipeline: boot Linux in QEMU (minutes),...

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2025

5 projects

Official year page

PeakRDL Exporter Plugin for CSR Visualization on Makerchip

The project aims to add an exporter plugin for PeakRDL that enables a high level visualization for control & status register (CSR) design using...

CodeProject page

Device-Under-Test Python Typing Stub Generator for cocotb tests

This project aims to create a tool that automatically generates Python typing stubs for the Device Under Test (DUT) in cocotb-based hardware...

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OpenRISC Linux Feature Development

​​Jump Label Implementation​​ aims to eliminate branch overhead in kernel code by dynamically patching JMP/NOP instructions at runtime using GCC's...

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Architectural Improvements to OpenPiton+Ariane for RISC-V Profile Compliance

This project aims to enhance the OpenPiton+Ariane architecture to progress toward RISC-V RVA23 profile compliance. The primary focus will be...

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Metro-MPI++

Modern RTL simulation is computationally expensive and often limited by single-node processing capabilities. This proposal aims to improve...

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2024

6 projects

Official year page

Transforming the OpenHW High Performance Data Cache into a High Performance Instruction Cache

Since CVA6/Ariane is highly modular by design, it is relatively easy to develop and integrate multiple L1 caches. Additionally, because CVA6/Ariane...

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Implementing RISC-V Cache Management Operation Extensions in OpenPiton

The project aims to integrate RISC-V Cache Management Operation (CMO) extensions into the OpenPiton processor framework. This integration will...

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Improving ATPG Fault Coverage in Fault

The semiconductor industry, driven by Moore's Law, continuously pushes the boundaries of integrated circuit (IC) technology, leading to...

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TinyParrot: A minimal BlackParrot RISC-V Multicore variant

TinyParrot is a BlackParrot RISC-V multi-core variant that aims to be small enough to fit onto educational FPGA development boards like the Pynq Z2....

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Integration of Silicon Compiler Microservices into the TL-Verilog Mode in VS-Code

This project aims to enable the seamless integration of the Silicon Compiler's hardware design tools and flows within popular development...

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Arcilator Vectorization

Add a vectorization support to Arcilator. An efficient vectorization pass will make Arcilator faster, as hardware designs often contain highly...

CodeProject page

2023

5 projects

Official year page

Circuit Visualization with Makerchip Platform

The Makerchip platform has added custom visualization support for circuit simulations, allowing for improved insights into microarchitectural...

CodeProject page

Enhancing OpenPiton+Ariane SoC With an Open-Source Advanced Interrupt Architecture (AIA)

The Platform Level Interrupt Controller (PLIC) is the de facto interrupt controller in RISC-V systems. However, the specification has intrinsic...

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Improving SDF support in Icarus Verilog

When you design a digital circuit, you want to make sure that all timings are correct, even post-layout. Therefore, the gate level netlist is...

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Enhancing OpenPiton+Ariane With a High-Performance Data Cache

As the demand for High-Performance Computing (HPC) continues to grow, there is a need for open-source solutions that can deliver the performance...

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Parameterized device layouts for GF180MCU

Throughout this project, I hope to gain a firmer understanding of TCL scripting and the backend working of parameterized devices and hopefully make...

CodeProject page

2022

8 projects

Official year page

Enhancing the Sootty Terminal-based Graphical Waveform Viewer

Sootty is a novel graphical waveform viewer targeted at modern terminals, however, it currently only supports VCD format and decimal system, not...

CodeProject page

IRSIM Dynamic Power Analysis and Other Improvements

Large digital designs are prone to consume lots of power and thus, a tool for power analysis is needed. There are two types of power analyses:...

CodeProject page

Improving Query Language Features in Sootty

My proposal aims to make Sootty, a CLI waveform viewer, a more utilitarian and intuitive tool to use, by adding features that I believe it would...

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Development Framework for Open MPW Shuttles

Efabless, Google, and SkyWater Technologies, through the Open MPW and ChipIgnite programs, provide free ASIC fabrication. To help streamline the...

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Logical Equivalence Checks with CIRCT

The CIRCT project is an open-source effort to develop Circuit Intermediate Representations, Compilers, and Tools by applying the MLIR and LLVM...

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Enhancing AnyCore, a superscalar RISC-V processor

AnyCore is an advanced superscalar processor developed at NC State University, designed to be highly configurable across parameters like issue width...

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1st CLaaS for PYNQ FPGAs

Utilizing cloud FPGAs prove to be very expensive and minor coding bugs could consume precious compute cycles and incur hefty bills. This proves using...

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TinyParrot: A minimal BlackParrot RISC-V Multicore variant

This project aims to shrink BlackParrot multicore to have a minimal variant called TinyParrot multicore. The main goal of this project is to get very...

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2021

11 projects

Official year page

Parallelising Verilog RTL Simulations Using MPI

This project will focus on a current problem in the Hardware community: The speed of RTL Simulations. These types of simulations are a necessary step...

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M-extension support for SERV

This project aims to design and integrate the integer “Multiplication and Division Unit (MDU)” with SERV core as a co-processor. The MDU will support...

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Bring up CV32E40P AI accelerator on FPGA

The open-source RISC-V instruction set architecture is gaining interest throughout industry and academia. One advantage of RISC-V is the ability to...

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Formal Verification of Mor1kx processor using Yosys-Formal tools

OpenRISC’s mor1kx is one of the old open source projects with more sophisticated and multi-core features. FuseSoC support for mor1kx makes it unique,...

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WARP-V Many-Core in the Cloud

The WARP-V is an open-source and highly configurable, adaptable, and flexible Core generator. It supports various ISA like MIPS, Open-Source RISC-V,...

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Black Parrot on Open-Source Google-Skywater 130nm node

Black Parrot is a tiny, modular Linux capable open-source processor core that encourages external contributions and strives for infrastructure...

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Block Based Circuit Design

Block-Based Circuit Design is a solution to counter the complexity of Circuit Design. We aim to develop and deploy a Block-Based TL-Verilog solution...

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Virtual FPGA Lab

Field-Programmable Gate Array(FPGA) is a hardware circuit that a user can program to carry out logical operations. FPGAs are beneficial for...

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Porting BaseJump STL to FuseSoC

The objective of this project is to port BaseJump STL to FuseSoC so that new projects can directly reuse these hand-optimized IP cores rather than...

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Multi-level TLB support for Ariane

The memory to CPU bottleneck is one of the fundamental and essential issues of commodity processors. With sweeply increasing computing speed,...

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TensorCore Extension for Deep Learning

Deep Learning continues to be a key application for a range of services nowadays - from autonomous vehicles to data centers and even in embedded...

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2020

4 projects

Official year page

AUTOMATING HARDWARE AND BITSTREAM VERIFICATION FOR PRGA WITH COCOTB

The goal of the project is to automate and augment the verification of the custom FPGA and the bitstream with Cocotb, an open-source framework for...

CodeProject page

Integrating ao486 with BYOC Framework

This project involves a heterogeneous-ISA system based on a BYOC (Bring Your Own Core) framework. This provides a cache coherent, manycore research...

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Integration of WARP-V with OpenPiton

WARP-V is an open-source and highly flexible and configurable CPU core with customisable ISA and pipelines written in the emerging...

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Enhancement in Warp-V and Optimization

The WARP-V RISC-V core generator was developed in 2018, it is the most-configurable, most-adaptable open-source RISC-V CPU core generator, taking...

CodeProject page

2019

7 projects

Official year page

Extend Librecores.org in terms of User Interactivity and Feedback

This project aims to develop user interactivity on the website through a full-fledged notification system and a platform to record user feedback. The...

CodeProject page

Microarchitectural enhancement of Ariane

This project is to add Microarchitectural enhancement of Ariane that is a popular open-source CPU core implementing the RISC-V ISA (instruction set...

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Analysis of WARP-V on FireSim with RocketChip

Analysis of the architectural performance of WARP-V using FireSim and RocketChip Chisel code. Adding WARP-V to RocketChip to utilize the capabilities...

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FPGA-Accelerated Web Applications

Building hardware requires access to costly tools and hardware, furthermore complexity in hardware design remains a deterrent force. FPGAs in the...

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Enhancing JuxtaPiton with X86 Support

JuxtaPiton is an architecture being developed at Princeton’s Parallel Group for heterogeneous ISA research. For this project, I will replace the...

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Continuous Integration for Hardware Projects on LibreCores CI

Librecores provides a platform to share projects and ideas, in the area of free and open source digital hardware design. Librecores CI is an...

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LLVM Code Generation for RISC-V Open Source GPU

Bespoke Silicon group at University of Washington is working on the second version of their open source RISC-V manycore processor. They are also...

CodeProject page

2018

6 projects

Official year page

Develop a Transaction-Level Verilog Component Library

Transaction-Level Verilog (TL-Verilog) is an emerging language extension to System Verilog, Has the ability to define flexible reusable components. ...

CodeProject page

Digital Filter Block Implementations in MyHDL and PyFDA Integration

Design and implementation of digital filters is essential for electronics engineers. Digital filter design in hardware usually is a two stage...

CodeProject page

Improve the LibreCores.org in terms of discoverability

LibreCores.org lists free and open source “IP Cores” on the website for the community to view and use. All listed projects are backed by a git...

CodeProject page

Formal verification of WARP-V processor

WARP-V is an emerging open-source CPU core generator for RISC-V CPUs. It benefits from the flexibility of Transaction-Level Verilog (TL-Verilog) to...

CodeProject page

BaseJump STL Hacker

I'm proposing the creation of a Math Library for BaseJump STL. Adding a set of routines that employ the CORDIC algorithm to implement directly and...

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Enable DEVSIM to simulate solar cells

DEVSIM is a TCAD (Technology Computer Aided Design) semiconductor device simulation software. TCAD tools are special simulation software that can...

CodeProject page

2017

4 projects

Official year page

Integration of OpenRISC Linux Port into OpTiMSoC

Open Tiled Manycore System-on-Chip (OpTiMSoC) is an open-source framework that allows one to design and prototype manycore-based platforms on FPGA...

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EDSAC Museum on FPGA

Electronic Delay Storage Automatic Calculator (EDSAC) is a first generation British computer commissioned in 1949. It was built by Maurice Wilkes and...

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Quality metrics for projects listed on LibreCores.org

LibreCores.org lists free and open source "IP Cores" on the website for the community to view and use. Currently the website extracts the project...

CodeProject page

Updating Sodor

Update riscv-sodor currently implemented in Chisel2 to Chisel3 along with that also update Privilege ISA Spec it complies to from 1.7 to 1.10 and...

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2016

3 projects

Official year page

QEMU port of OpenRISC

QEMU is a free and open virtual machine software that can be useful for the OpenRISC community for testing and teaching software development on the...

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Yosys Tools: Automatic schematic generation for web browsers

Schematics are a great way to understand electronic circuits, and specially when we are using high level descriptions, it becomes essential that we...

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RISC-V port to Parallela

With this proposal I hope to benefit the open-source hardware enthusiast community with work related to the incredible Parallela board used by...

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