Programming languages

CHIPS Alliance

Open source IP, tools & standards for ASIC/FPGA

ASICchiselfpgahardwarerisc-vsystemverilog

Organization website

Participation history

3 GSoC years

2024 2023 2022

2024

4 projects

Official year page

Support Zvk in T1 (RISC-V Vector coprocessor)

Our "Support Zvk in T1" project aims to upgrade the T1 processor by adding Zvk, a cryptographic feature from the RISC-V architecture, enhancing its...

Code Project page

Create a GDS reader/writer in OpenROAD

I, Muddassir Ali, a final-year Computer Systems Engineering undergraduate student from Pakistan, aim to contribute to the OpenROAD project by...

Code Project page

Relational Framework for Prompt-based Automatic Layout Generation with Glayout

The proposal seeks to build upon an existing relational framework that facilitates the generation of DRC-compliant analog layouts through...

Code Project page

GDS Reader/Writer in OpenROAD

This Project adds GDS input and output features to OpenRoad. It would replace the current GDS manipulation scheme, which is through Klayout, and...

Code Project page

2023

5 projects

Official year page

Implement Zc RISC-V ISA Extension in Rocket Chip

This project aims to add support for the RISC-V Code size reduction extension (Zcb, Zcmp, Zcmt) to Rocket Core and perform the architectural testing...

Project page

DSP hard block integration in F4PGA

F4PGA is an open-source FPGA toolchain designed as a free alternative to proprietary computer-aided design tools like Xilinx’s Vivado. Currently,...

Code Project page

1st CLasS (Custom Logic as a Service) for Local FPGA Deployment using F4PGA

1st CLasS framework is an open-source project that deals with the deployment of a custom kernel on AWS EC2 instance cloud FPGAs with fully automated...

Code Project page

Implementation of a Common Python Framework for OpenFASoC Generators

OpenFASoC is a project focused on creating fully automated user specifications to GDS generation flow using open-source tools. OpenFASoC uses tools...

Code Project page

Makerchip Flows: A Suite of EDA Flow integrations for TL-Verilog ecosystem

Makerchip Flows aims at developing EDA flows for TL-Verilog leveraging Edalize backend, for open source tools/flows like yosys, Openlane, F4PGA,...

Code Project page

2022

3 projects

Official year page

Verible SystemVerilog Preprocessor

The objective is to create a SystemVerilog preprocessor for Verible (which is a suite of SystemVerilog developer tools, including a parser,...

Code Project page

Improving the automatic layout generation of the mixed-signal temperature sensor block in OpenFASOC

OpenFASOC is an open-source framework for autonomous generation of optimized integrated circuit blocks given user specifications. It is a growing...

Code Project page

Development of a smart CI workflow to test analog block functionality and performance in OpenFASOC

OpenFASOC, an automated SOC generator, is enabling chip enthusiasts to develop circuits/macros with a software approach. Circuits must not only be...

Code Project page