2022
0 projects

Science and medicine
open source cinema
0 projects
5 projects
The project's main goal is to create a Simulation/Emulation of the CMV12000 sensor currently used in the AXIOM Beta. The HDL could be placed as a...
nMigen is an HDL toolkit implemented in the Python programming language. By using nMigen instead of traditional HDLs like Verilog or VHDL, gateware...
The AXIOM recorder software can record moving images from axiom cameras via either USB3 or Ethernet. Currently, that software is only a CLI tool that...
The AXIOM Remote is a device used to control the AXIOM Beta range of cameras. The aim of this project is to develop an automated test system to test...
Firmware as the name suggests is a bridge between User and hardware/features of Axiom Remote. Hence, there is a need for Firmware to follow good...
4 projects
The Axiom Beta currently uses CMV12000 which is a high-speed CMOS image sensor with 4096 by 3072 pixels.The pixels are located at different channels...
Apertus-Axiom Beta utilizes two Lattice MachXO2s to expand the IOs interfaces for the main processing unit (ZYNQ-SoC). The channel comprises two LVDS...
The aim of this project (task #T729) was to make a Linux Kernel Driver to program and debug the Lattice MachXO2 FPGAs present in AXIOM Beta. These...
4 projects
Working on the AXIOM Remote hardware
Implementing gearwork and communication interface for the USB 3.0 plugin module, designed by apertus° Association, for streaming live 4K 12-bit video...
The project aims to extend the capabilities of the control daemon so as to provide smooth communication between the Graphical controller the Web...
Implementation of JPEG 1992 lossless encoder core in the FPGA.
4 projects
The project is a result of the lab task T951 which aims at comparing and finding the right containerization system suitable for AXIOM Beta camera...
I am applying for the task T722, listed on Phabricator (https://lab.apertus.org/T722). I have to implement several debayering algorithms (by myself...
The proposal describes detail description for the design of real time focus peaking kernel in VHDL for FPGA. It covers all aspects of the image...
The AXIOM Beta features a small program called cmv_hist3 that calculates raw histogram value from current image in real time processing pipeline. The...
1 project
The main idea of this project is to design a high efficiency buck converter that will supply the Apertus AXIOM camera system. Its main feature is the...